State machines built from integrated circuits on semiconductor substrates need to be hardened against radiation to prevent soft error event that occur when a radiation particle travels through the semiconductor. This is particularly true if the state machine is to operate in high radiation environments such as outer space. A radiation particle traveling through the semiconductor substrate may cause a transient voltage glitch, i.e., a single event transient (SET) or may cause a sequential state element (SSE) to store the opposite state, i.e., a single event upset (SEU).
One technique for preventing the effects of high energy radiation is to provide to build a triple modular redundant (TMR) pipeline circuit with TMR SSE. In this manner, if a radiation strike result in a soft error in one copy of the pipeline circuit, the redundant SSEs in the other two copies of the pipeline circuit can correct the soft error in the affected SSE through TMR self-correction techniques. However, the power and area impact of the TMR SSEs is substantial due to the number of components (e.g., the number of field effect transistors (FETs), needed to implement each of the redundant SSEs in the TMR SSE. Accordingly, SSE designs are needed, which allow for TMR correction while consuming as low power and area in an IC as possible.